(a) Field of the Invention
The present invention relates to a method of forming semiconductor patterns. More specifically, the present invention relates to a spacer defined double patterning (SDDP) process using a PEALD spacer oxide deposition process having trimming action.
(b) Description of the Related Art
Due to the limit of resolution of the immersion ArF lithography, the method of Double Patterning is used in the chip patterning process for 3× nm half pitch and below.
In the art, the method of Spacer Defined Double Patterning, as represented in FIGS. 1A-1D, is as follows. As shown in FIG. 1A, photo resist template patterns 2 are formed on top of a bottom layer 1. Here, the line width and the line spacing are in a ratio of about 1:3. As shown in FIG. 1B, an oxide spacer conformal 3 is deposited on the photo resist template patterns 2. Here, the thickness of the oxide film is equal to the width of template line.
Next, as shown in FIG. 1C, the deposited spacer oxide film 3 is etched back by RIE (reactive ion etching) such that film on the upper and bottom surfaces of pattern are removed and spacers 3a are formed on the side wall surfaces of the photo resist template patterns 2.
Then, as shown in FIG. 1D, the photo resist template patterns 2 remaining between the spacers 3a are removed by selective etching and the bottom layer 1 is etched by using the spacers 3a as hard mask.
As single exposure lithography is very challenging in achieving 3× nm line widths and below, in the art a photo resist shrink step can be applied prior to the deposition of the spacer material as shown in FIG. 2A to FIG. 2E. Firstly, first photo resist template patterns 22 are formed on top of a bottom layer 11 as shown in FIG. 2A. Here, the ratio of line width X1 to spacing in between the lines of the first photo resist template patterns 22 is 1: A, wherein 1≦A<3. The photo resist template patterns 22 are trimmed so that the line width of the photo resist template patterns 22 shrinks to form the second photo resist template patterns 22a as shown in FIG. 2B. Here, the line width X2 is about ⅓ of the line spacing of the second photo resist template patterns 22a. The trimming can be performed by an oxygen plasma or by thermal annealing in an inert ambient or in an oxidizing or reducing ambient. The trimming can be performed in a separate chamber or in-situ, in the same chamber in which the spacer oxide deposition is performed without removing the substrate from the chamber in between the trimming and deposition steps.
As shown in FIG. 2C, an oxide spacer conformal 33 is deposited on the second photo resist template patterns 22a. Here, the thickness of the oxide film 33 is equal to the width of the second photo resist template patterns 22a. The deposited spacer oxide film 33 is etched back by RIE (reactive ion etching) such that the film 33 on the upper and bottom surfaces of patterns 22a are removed and film on the side wall surfaces of the patterns 22a remain to be spacers 33a as shown in FIG. 2D. Then, as shown in FIG. 2E, the second photo resist template patterns 22a remaining between spacers 33a are removed by selective etching so that the spacers 33a remain and then the bottom layer 11 is patterned by using the spacers 33a as a hard mask (HM).
Through the above described sequence, the number of lines having the same width as the lines of the template after trimming is doubled and the pitch is halved. Instead of a spacer oxide, an alternative material, such as an oxynitride or a nitride material with suitable properties, could be selected.
If the target Critical Dimension of lines is getting smaller than 30 nm, it will become difficult to control the uniformity of the amount of shrinking of such a photo resist shrink step or trimming step. Furthermore, there is a higher chance of patterning failure due to the leaning or collapsing of photo resist line due to the weak footing of the photo resist line when the photo resist line becomes narrower by the trimming.